FIG. 1 is a cross-section view schematically showing a memory cell described in an article of Jing Wan et al. entitled “Progress in Z2-FET 1T-DRAM: Retention time, writing modes, selective array operation, and dual bit storage” published in 2013 in Solid-State Electronics, volume 84, pages 147 to 154.
The memory cell comprises a silicon layer 1 resting on an insulating layer 3, itself resting on a silicon substrate 5. A heavily-doped P-type drain region 7 (P+) and a heavily-doped N-type source region 9 (N+) are arranged in silicon layer 1 and are separated from one another by a non-doped region 11 of silicon layer 1. On the side of drain region 7, the memory cell comprises an insulated front gate electrode 13 (insulator 15) resting on a portion only of region 11 of layer 1. Insulated gate 13, drain region 7, and source region 9 are connected to respective nodes G, D, and S.
In operation, a −2-V negative bias voltage is applied to substrate 5 and a reference voltage, the ground, is applied to node S. To read or write one or the other of two binary values from or into the memory cell, control voltages are applied to nodes D and G in the form of pulses. The values of the control voltages and the operation of the memory cell are described in further detail in the above-mentioned article.